Needing more than a spark test?

On the circuit I sent, if you short circuit the capacitor, the output changes polarity, and messes up.

Given that you are cautioning what may happen in a practical build, should I use preemptive caution, and include 0603, or 0805 pads, with 0Ω links, just in case on power-up, one needs to introduce a capacitor or two?
Yes. I would.

BTW, LTC6268-10's are back ordered or out of stock at Digikey and Mouser. Strangely, Digikey says they have 2K in stock, but won't sell me 2. I tried ordering 2 and was told an anticipated 11 March delivery. LTC6268's are not available at Digikey, they have 0.

LTC6269's are available only in the DFN-10 package right now, which are tough to solder. I guess I could try with my hot air gun.
Curiously, I can buy LTC6269-10's and they can be bought in MSOP8. Crazy world. I could go all LTC6269-10's and spread out the gain, or just not use one of the stages.

Found something that seems to work, but I am skeptical at this point. LTC6269-10, followed by two LTC6269 devices. DC coupled for the first two stages. Still playing with the last stage. Trying to get rid of 1.35mV offset. To eliminate it I need to introduce -6.81uV to the positive terminal of the last stage. Seems like that node would be touchy and wander with temperature.
1675444685621.png
0.1pA generates 233uV pulse (2.5V/2^16 = 38.15uV) or 6.1 counts. 1000pA generates 2.332V or 61131.98 counts. 4 decades. This circuit is very sensitive to any offsets, and capacitance. Be fun to try, but it may oscillate like mad. I'm a bit uncertain how to physically arrange the diode and it's bias circuit. Can you guide me on this? Is it just replacing the current sources, resistor and C1 with the following?
1675448541709.png
 
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Yes. I would.

BTW, LTC6268-10's are back ordered or out of stock at Digikey and Mouser. Strangely, Digikey says they have 2K in stock, but won't sell me 2. I tried ordering 2 and was told an anticipated 11 March delivery. LTC6268's are not available at Digikey, they have 0.

LTC6269's are available only in the DFN-10 package right now, which are tough to solder. I guess I could try with my hot air gun.
Curiously, I can buy LTC6269-10's and they can be bought in MSOP8. Crazy world. I could go all LTC6269-10's and spread out the gain, or just not use one of the stages.
The supply situation is the same here in UK. I actually have a couple LTC6268-10's ordered earlier. The LTC6268IS8 500MHz GBW version would do just as well, but the supply situation is the same for both kinds. If you are stuck for it, I can send you one of those I have. If can get my board act together, I would try putting it on the board, and send the ensemble.

I specifically went for a single opamp in S8 package because I want to use the tracking shown on Figure 8 on pages 15, and Figure 12 of Page 17 of the datasheet.. I want to include the transimpedance guard ring, because when you start talking 0.1pA, the currents across the FR4 from all sorts of places will compete with the 2fA input bias current.

It may be that if LMC6269 dual opamp in the S6 package is available, one can use a couple of them for any ramaining opamps in the circuit, but I think the only place one really needs the performance of the LTC6269-10 is for the first stage wideband TIA. We may have more freedom on choosing for subsequent stages if supply is yuk
Found something that seems to work, but I am skeptical at this point. LTC6269-10, followed by two LTC6269 devices. DC coupled for the first two stages. Still playing with the last stage. Trying to get rid of 1.35mV offset. To eliminate it I need to introduce -6.81uV to the positive terminal of the last stage. Seems like that node would be touchy and wander with temperature.

0.1pA generates 233uV pulse (2.5V/2^16 = 38.15uV) or 6.1 counts. 1000pA generates 2.332V or 61131.98 counts. 4 decades. This circuit is very sensitive to any offsets, and capacitance. Be fun to try, but it may oscillate like mad. I'm a bit uncertain how to physically arrange the diode and it's bias circuit. Can you guide me on this?
You are doing just great!
I am thinking it's quite hard to able end up working with 6 counts. That would be fantastic, but I have my doubts! Even when I was trying hard, I struggled to to get 16-bits counts below 80, and when I started getting better at it, I did get a count as low as 39. I don't know what they do in the test labs, but it must be something special.

Regarding offsets, drift, etc. -36pV !
I have attached a file with one little modification in it.
For offset at the output, is -36pV in the middle of 0.2V good enough for us?
I think that can be had even after a additional last stage delivering 2V.

There is still the spare LTC6269 left over, handy to give a gain of 10 to take the output up to 2V, but for the moment, check out this one delivering 0.2V from a 100pA pulse. I added the integrator, with a time constant that does not have a chance against a 20uS pulse.

What I am saying is it will likely not do that in the real build. The S/N ratio of the ADC is 91dB. The S/N ratio of what we may be seeing as racket from a photodiode, I don't know yet. The offset we are talking about is (36pV) and would be -214dB down. It will be below the noise, and the count will be jangling about down there.

Of course, what if it is not a max sized pulse? How small can we go before we start to worry about what fraction is offset? Anyway, I am thinking that an integrator driven offset stabilization loop using a spare op-amp is a cheap dodge, and I am just waiting to get tripped up on it.

[Edit: Sorry, I have not yet answered you regarding the bias. I will get back to you after dinner, which has been called :) ]

TIA_Amp3.png
 

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The supply situation is the same here in UK. I actually have a couple LTC6268-10's ordered earlier. The LTC6268IS8 500MHz GBW version would do just as well, but the supply situation is the same for both kinds. If you are stuck for it, I can send you one of those I have. If can get my board act together, I would try putting it on the board, and send the ensemble.

I specifically went for a single opamp in S8 package because I want to use the tracking shown on Figure 8 on pages 15, and Figure 12 of Page 17 of the datasheet.. I want to include the transimpedance guard ring, because when you start talking 0.1pA, the currents across the FR4 from all sorts of places will compete with the 2fA input bias current.

It may be that if LMC6269 dual opamp in the S6 package is available, one can use a couple of them for any ramaining opamps in the circuit, but I think the only place one really needs the performance of the LTC6269-10 is for the first stage wideband TIA. We may have more freedom on choosing for subsequent stages if supply is yuk

You are doing just great!
I am thinking it's quite hard to able end up working with 6 counts. That would be fantastic, but I have my doubts! Even when I was trying hard, I struggled to to get 16-bits counts below 80, and when I started getting better at it, I did get a count as low as 39. I don't know what they do in the test labs, but it must be something special.

Regarding offsets, drift, etc. -36pV !
I have attached a file with one little modification in it.
For offset at the output, is -36pV in the middle of 0.2V good enough for us?
I think that can be had even after a additional last stage delivering 2V.

There is still the spare LTC6269 left over, handy to give a gain of 10 to take the output up to 2V, but for the moment, check out this one delivering 0.2V from a 100pA pulse. I added the integrator, with a time constant that does not have a chance against a 20uS pulse.

What I am saying is it will likely not do that in the real build. The S/N ratio of the ADC is 91dB. The S/N ratio of what we may be seeing as racket from a photodiode, I don't know yet. The offset we are talking about is (36pV) and would be -214dB down. It will be below the noise, and the count will be jangling about down there.

Of course, what if it is not a max sized pulse? How small can we go before we start to worry about what fraction is offset? Anyway, I am thinking that an integrator driven offset stabilization loop using a spare op-amp is a cheap dodge, and I am just waiting to get tripped up on it.

[Edit: Sorry, I have not yet answered you regarding the bias. I will get back to you after dinner, which has been called :) ]

View attachment 436038
You are five hours ahead of me, so by all means have your dinner!

I saw the offset correction circuit in a few tech notes. They obviously rely on the fact that the pulse density is low. If you had brighter sources, or more of them, the correction might be askew. When it works, it should be ok. Just wondering out loud how easy the integrator would be to set up. Probably would need a pot on it to dial it in. Analog integrators are notorious for a reason, due to running away from integrating offset and bias. But it is worth a try. The amplifier has been paid for if one is buying LTC6269's...
 
This circuit simulation is very sensitive to the shape of the pulse. I tried a trapezoidal pulse and the output of the first stage totally misbehaves. Rise time 700ps, fall time 3us, on time 2ns, repetition time, 50us. First stage rails, even with a pulse current of 1aA! Probably have to change the default settings, but wasn't expecting to see railing behavior, especially at a time that was not related to the stimulus waveform.

In contrast, the single exponential pulse was well behaved. But to see the integrator circuit work, I want to see lots of pulses... Tough to see if an integrator is working with a single pulse. Wish one could string together exponential pulses...
 
@graham-xrf simulated your circuit for 10ms, and can see the damped but sinusoidal decay of the integrator output. This is for a single 1nA exponential pulse in your model. It takes on the order of 5ms to decay. Other pulses occurring during this time may have a damped sinusoidal error on them. For a big pulse, the error doesn't seem to correct to zero. We may care (or may not) if we are affected by the bobbling of the baseline, if it is near our thresholds for integrating the pulse energy. If the pulse base bobs up and down, it can look like more energy. But in fact it is simply noise, which spreads out our pulses.
1675457413864.png
I'm sure there is a way to fix up the integrator to make it slightly better behaved.
 
This circuit simulation is very sensitive to the shape of the pulse. I tried a trapezoidal pulse and the output of the first stage totally misbehaves. Rise time 700ps, fall time 3us, on time 2ns, repetition time, 50us. First stage rails, even with a pulse current of 1aA! Probably have to change the default settings, but wasn't expecting to see railing behavior, especially at a time that was not related to the stimulus waveform.

In contrast, the single exponential pulse was well behaved. But to see the integrator circuit work, I want to see lots of pulses... Tough to see if an integrator is working with a single pulse. Wish one could string together exponential pulses...
Our pulse rate is hardly promising to be spectacular. I feel a huge rush of pulses might not be our problem :)
Now that we have the simulator to help us, we might well be running into some of the LTSpice setups and tricks they got up to to make it generally useful for folk designing power supplies. Sure, we have to be careful.

I do have "other" pulses. There is one which is a PWL type description which sprawls the length of the circuit schematic and beyond.
Try not to laugh!
PWL(1uS 0pA 1.25uS 1.5pA 1.5uS 3.5pA 1.60uS 4.0pA 1.75uS 5.7pA 1.9uS 7.0pA 2.0uS 8.5pA 2.1uS 10pA 2.25uS 13pA 2.5uS 16.5pA 2.75uS 21.0pA 3uS 24.0pA 3.5uS 25pA 4.0uS 24.0pA 4.5uS 21.5pA 5uS 18.5pA 6uS 14pA 7uS 10pA 8uS 7.0pA 9uS 5.0pA 10uS 3.0pA 11uS 2.25pA 12uS 1.5pA 13uS 1.0pA 14uS 0.5pA 15uS 0.0pA)

I only used it because I was trying for fast simulations. I settled for the exponential version because it looked exactly like the pulse expected, and even like the one Mark has seen on a scope.

What really happens?
Just how big of a pulse is going to happen? I crashed and burned all over the place on this one. I tried to imagine a reverse biased PIN diode, looking like a 85pF capacitor, and then 60KeV of photon energy arrives. So how exactly do we figure how many electrons that would be? We don't know the voltage at any point, and we would only be good if we had a current and a time.
Yes, those 60,000 little eVs each had 1.602176634 × 10−19 coulombs
If it were at 1V, that would be 9.613059804e-15 Joules. We can use (V*V^2)/2. Or we can say that same number of coulombs went into the 85pF.
I went for the "triangle" pulse area equivalent approximation over 13uS as having the same energy.

I won't bore you all with my foray into into how I thought the calculation should go, and how it went. Eventually, I took the "other" approach. When you have looked at enough TIA circuits, and read the whole book attached, you start to zero in on what is reasonable.

Can it really be done in practice? The very first page shows a LTC6268-10 TIA amplifier for high speed optical communications. 210MHz! If it can do that, then it is absolutely what we need to run at higher gain, and lower bandwidth, and I have not found much other devices that have this potential, certainly not a LMC662! A gain of 20,000 is 86dBΩ. That is huge for one stage! I know I have been putting hundreds of KΩ in there in some of my tryouts, but we don't have to do that. Any subsequent voltage amplifier stage multiplies the gain we get here. Much better to get the gain in sensible stages.

Yes - we know the problems of having that much gain available within a few millimetres of circuit board, able to run at VHF. More serious might be the gain oscillating away at audio frequencies, and burning out the chip! We now have all it takes to make it work for us, for not so many $bucks. We can have a huge first stage gain, and limit the bandwidth. It can't go at VHF if we have a couple of hundred kΩ in there!

I don't think it will have any trouble reproducing a 10uS wide pulse, even if we are having a hard time inventing one, or a stream of them, to use in a simulation.

LTC6268-10 TIA amp.png
 

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Our pulse rate is hardly promising to be spectacular. I feel a huge rush of pulses might not be our problem :)
Now that we have the simulator to help us, we might well be running into some of the LTSpice setups and tricks they got up to to make it generally useful for folk designing power supplies. Sure, we have to be careful.

I do have "other" pulses. There is one which is a PWL type description which sprawls the length of the circuit schematic and beyond.
Try not to laugh!
PWL(1uS 0pA 1.25uS 1.5pA 1.5uS 3.5pA 1.60uS 4.0pA 1.75uS 5.7pA 1.9uS 7.0pA 2.0uS 8.5pA 2.1uS 10pA 2.25uS 13pA 2.5uS 16.5pA 2.75uS 21.0pA 3uS 24.0pA 3.5uS 25pA 4.0uS 24.0pA 4.5uS 21.5pA 5uS 18.5pA 6uS 14pA 7uS 10pA 8uS 7.0pA 9uS 5.0pA 10uS 3.0pA 11uS 2.25pA 12uS 1.5pA 13uS 1.0pA 14uS 0.5pA 15uS 0.0pA)

I only used it because I was trying for fast simulations. I settled for the exponential version because it looked exactly like the pulse expected, and even like the one Mark has seen on a scope.

What really happens?
Just how big of a pulse is going to happen? I crashed and burned all over the place on this one. I tried to imagine a reverse biased PIN diode, looking like a 85pF capacitor, and then 60KeV of photon energy arrives. So how exactly do we figure how many electrons that would be? We don't know the voltage at any point, and we would only be good if we had a current and a time. I went for the "triangle" pulse area approximation over 13uS.

I won't bore you all with my foray into into how I thought the calculation should go, and how it went. Eventually, I took the "other" approach. When you have looked at enough TIA circuits, and read the whole book attached, you start to zero in on what is reasonable.

Can it really be done in practice? The very first page shows a LTC6268-10 TIA amplifier for high speed optical communications. 210MHz! If it can do that, then it is absolutely what we need to run at higher gain, and lower bandwidth, and I have not found much other devices that have this potential, certainly not a LMC662! A gain of 20,000 is 86dBΩ. That is huge for one stage! I know I have been putting hundreds of KΩ in there in some of my tryouts, but we don't have to do that. Any subsequent voltage amplifier stage multiplies the gain we get here. Much better to get the gain in sensible stages.

Yes - we know the problems of having that much gain available within a few millimetres of circuit board, able to run at VHF. More serious might be the gain oscillating away at audio frequencies, and burning out the chip! We now have all it takes to make it work for us, for not so many $bucks. We can have a huge first stage gain, and limit the bandwidth. It can't go at VHF if we have a couple of hundred kΩ in there!

I don't think it will have any trouble reproducing a 10uS wide pulse, even if we are having a hard time inventing one, or a stream of them, to use in a simulation.

View attachment 436046
It's been a struggle to understand the nature and magnitude of the pulse. Lots of calculations, and assumptions. The assumptions, if false, totally destroy the validity of the calculations. I fear that I can't contribute much in this area, save for checking computation, and perhaps doing units / dimensional verification. Simply don't have an atomic physics back ground...

As for the piece wise linear waveform hack, I admire your perseverance! Wish there was a native and simple way to create these pulses. I can say my simple trapezoidal pulse results were not encouraging at all.

I have read that it is better to get as much gain into the first TIA stage as possible, as it maximizes the SNR. Once the SNR is set, it is up to us to maintain it, hopefully only squandering a couple of dB here and there due to processing. So if at all possible, I'm trying to use a value like 240k in the front end.
 
It's been a struggle to understand the nature and magnitude of the pulse. Lots of calculations, and assumptions. The assumptions, if false, totally destroy the validity of the calculations. I fear that I can't contribute much in this area, save for checking computation, and perhaps doing units / dimensional verification. Simply don't have an atomic physics back ground...

As for the piece wise linear waveform hack, I admire your perseverance! Wish there was a native and simple way to create these pulses. I can say my simple trapezoidal pulse results were not encouraging at all.

I have read that it is better to get as much gain into the first TIA stage as possible, as it maximizes the SNR. Once the SNR is set, it is up to us to maintain it, hopefully only squandering a couple of dB here and there due to processing. So if at all possible, I'm trying to use a value like 240k in the front end.
About the SNR. I have spent a career wringing the last bit of signal out of GHz front ends where we would care about the noise coming from the day temperature of a feed horn. I found out long ago that it is a mistake to simply pile on all the gain in the first device. You may have used cascade analysis yourself. There are online calculators.

Once you have more than about 26dB (that is power gain 10log(gain), the SNR is locked in, but not enough.
If you have it as high as 44dB, then you can afford 10 or 15dB of noisy loss attenuation before the noise contributions from passive stuff before the next amplification stage starts to catch up with the (amplified) noise from the first stage. The SNR becomes "locked in".

I have several times had to show people who were paid lots more than I ever saw, and who I thought should know better, how to get gain distribution right. They were allocating dBs here and there, and discovering the father and mother of unwanted spurs and inter-modulation distortion, having run out of dynamic range.

Even with half the gain of the LTC6268-10 example, the noise of the input will have been amplified so high that there is not much a later stage can do to harm it. Of course, the signal will have been amplified by the same amount. The SNR is "preserved".
 
I got the inter modulation product lesson in cascaded designs long ago in a radar design in my late twenties. I learned the lore of the "low NF 10 dB amplifier". But have to say, I have seen numerous examples of so much "dumb stuff" added, that the SNR plummeted due to improper cascade design. It does happen, and by supposedly smart people.

All that aside, we still need to come up with a decent, idiot proof TIA design that operates with little to no tweaking, that works over process voltage and temperature. Fortunately, we don't need to deal with huge temperature ranges, but, it can't drift out of "compliance" while packaged away in whatever the enclosure is. At the moment, speaking only for what I have designed, I don't think I am there yet.
 
Here's a different approach to the input circuit, based on the idea that a charge amplifier, not a TIA, can accomplish much the same thing. The charge coming out of the detector is dumped into a capacitor that integrates the charge. Q = CV so V = Q/C (and the "gain" element is a noise-free capacitor!). The resultant voltage is input to a high-impedance (but not particularly high bandwidth) amplifier. I did have to extract a bit of current to reduce the offset but I think a secondary lowpass-filtered feedback loop could take care of that.

The risetime and decay time are comparable to other approaches but neither one of them are dictated a whole lot by the amplifier GBW. Within reason, anyway. Is it, really, a TIA or is it a charge amp??

This approach is based on my recollection of a high speed integrator using an all-passive RC network.

For expediencies sake I _did_ reduce the bias voltage to zero, so the offset current really will need to be greater to compensate for the PIN diode's dark current. Feedback will take care of that. Or maybe a digital pot that periodically acts to null the offset.

I'm throwing this out there to suggest that there may be different ways to look at the detector circuit, and (perhaps) allow the use of parts that have a lower GBW compared to some high GBW parts that seem to be in short supply.

Admittedly, this particular implementation is aimed at the Theremino approach where the pulse is heavily filtered: but in this case the peak voltage is pretty much determined by the charge coming out of the detector divided by the load capacitor. No ambiguity regarding the relationship between the current coming out of the detector and the voltage coming out of the amplifier chain.

I can't say this is a perfect solution because there still is the possibility of pulse overlap causing problems but that's going to be an issue regardless of what the front end looks like.

Screenshot_2023-02-03_20-52-49.png
 
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