TIA Gain Bandwidth Analysis
Other casual HM readers will get well turned off by this, but I wanted to do a walk-through. It delves the electronic technical using currents of less than 100,000 electrons in about 10uS, and is way far away from making hot metal lathe chips and surface metrology!
A little passing check on the issues of what it takes to extract the signal in a credible way.. motivated by the Pocket Geiger 5.
The circuit looks so simple, but I can tell you almost none will "just work" easy.
I am now rather further along into A/D conversion selection, costs, and weighing up things like multiple supply voltages, including those that would trash the amplifier front end op-amp. Some good affordable ADCs need external references and reference buffers vs ADCs with the reference built in. I try for using the full Vref range, even with differential inputs, and very low noise high bandwidth negative voltage generators. The circuit fragments shown here are not the final, just test circuits to investigate what it takes to believe that the pulse was preserved and measurable, instead of some smudged artifact.
The LTSpice test example shown compares a lower end photonic signal of
500pA (which may be unsuitable as too big, but it compares to Id=2nA dark current), with a much bigger
80nA signal (which may be unsuitable for being too small, but we already hit the rail)! That's OK. One could make the minimum signal smaller, and increase the gain, to no point, but stay with these for now.
It took some work getting the LTSpice app even to make these. To get the tool to work, I set the Absolute Current Tolerance to 5E-13A, and the Absolute Voltage Tolerance to 1e-7V. It may need more tweaking. I set Gmin to 1E-14, and that may yet not be small enough to compete with FET input currents in femtoamps.
This time, I use an op-amp circuit where the first stage "gain" is not defined by a silly feedback capacitance in integrator mode, in parallel with 66Meg resistor that may as well not be there! The gain is now defined by the feedback resistor. To be able to sustain a first stage gain as high as 510k, and still hope to follow to follow a pulse that will be over in 10uS, you need an amplifier having GBW of 300MHz and more. The LTC6269 is a dual op-amp, with GBW of 350MHz in S8 size package, or 500MHz in MSOP. I don't know how the LTSpice model can know how to choose.
I fully explored the value of C2, across the feedback resistor. At 0.2pF, and 2MEG , it oscillates madly. 0.5pF stops the madness, but still overshoots and distorts. 1pF is safe, and is already introducing bigger phase delays. The delay seen is near 1uS.
I fully explored the value of C3, which I use to take out the offset of the dark current. from 1pF to 1000pF. The signal captured gets bigger, and is running out of advantage at 600pF. I put a 1nF value there, and I would consider making it smaller.
The higher range for A/D converters chooses between 3.3V supplies, and 5V supplies. Choosing the larger, the Vref will be 4.096V from a low noise, buffered, bandgap reference.
In the circuits shown, the 500pA current delivers 26mV. Without the full noise analysis, I don't know yet if that is 26mV competing with highly amplified noise, but I think it, as design example, is OK, it being already
-101.2dB down for a devices which would only manage no more than
96dB dynamic range anyway, and more likely to be nearer 90dB. This also lets us know that using a 2.048V reference only halves the small signal, and we are already 10dB below. THere would be no advantage.
[ These dBs are 20*Log10(voltage ratio) ]
We could make the first stage gain a bit less, and the second stage gain a bit more, but to no point. We should make the gain suit the minimum signal we can have tickle the LSB of the A/D converter, starting with 4.096V. We will have a maxed out gain distribution that can see to the noise floor.
Driving ADCs
One needs a low impedance forcing signal to settle the speed of the pulse at the ADC input, which itself is going to take current suck right then. A differential driver, if it has gain, would allow we operate the TIA at lower gains, potentially allowing cheaper, lower GBW op-amps.
I get it that this stuff will look like gobbledegook to some, and is, to be truthful, relatively amateur level electronics design, but I wanted to take the mystery out of just about every XRF-type Geiger counting circuit I have seen so far, starting with Theremino.