Needing more than a spark test?

[graham-xrf]

Make sure your "can" is crimped shut or formed from one piece. If it is soldered, the bottom could fall off! I don't know how easy it is to melt in a "tin can", I have only melted lead in a small cast iron bowl like thing, or in a proper melting pot. Just recently found a small graphite crucible, that I probably used for melting lead. Wishing you a boring and unexciting time casting.

Those around me who do not reasonably understand me. What I get up to need not even begin to come out of the "boring" category before it apparently confirms all prejudices, and brings all manner of "reactions". Even when the outcome is entirely useful, praiseworthy, and a total triumph, I never expect more than a grudging response about whether the endeavor was "worth it". Like in the Mark Harmon movie ("For All Time" 2000), I should have been doing melting stuff in 1896.

Think it will take a bit to get the initial melt going. Once you have some liquid lead, slowly feed in more metal into the can. Flux if the lead is really looking dross like. You can use a small bit of wax from a candle for this. It will smoke and then burn. Definitely an outdoor and well ventilated activity.

Thanks for the advice. I plan to use a butane fueled cooker ring, with vermiculite (ex woodburner) insulation arranged around it. I could blast it from the top with oxy-fueled torch, but I don't think that will be needed. At most, I think some augment heat from the top can be applied with with a plumbing torch. One thing that may still have lots to affect this is that it's still chilly outside, about 7C, and there is a high wind!

The can is definitely roll-rim sealed. I will cut it about halfway up it's length.

Yes, I know about the smoky candle method of using carbon to collect contaminants.

I also have a can of borax, and (not the same stuff), I have some boric acid. Borax is a common fluxing stuff, most used to keep oxygen from getting at a weld. I don't know whether either would be useful when melting lead.

The least wanted outcome is to get the steel so fluxed it "wets", in effect lead soldering the chunk to the can, like it was a piece of gutter!

 

[graham-xrf]

Looking at the thermometer thingy magnet-attached to my ClearView woodburner in the living room, it occurs to me I could just put the right weight of lead, plus maybe about 2cm of candle, into the (half of) a steel can, stood between a couple of nice oak or ash logs, and .. wait?

Yes - those who think I don't want to be outside in the cold high speed winds trying to keep a butane camp cooker alive have got it absolutely right!
That is what a decent chimney with excellent flue liner is for!

 

[RJSakowski]

Finally, something I can speak to. The three of you were beginning to give me an inferiority complex with all your technical talk. PSU's and ADC's and zero offsets, oh my!

You will have no problem melting lead. I often use cans from veggys for molds. I made a melting pot from a veggy can by running a coat hanger loop though a couple of holes. The lead will melt easily with your camping stove or with a propane torch. I don't usually bother with flux, I just scrape off the dross until I have clean metal. If you want to use flux, soldering flux will work. If you don't use flux, there is no need to work outside.

 

[WobblyHand]

Spent some quality time wrestling with KiCAD. Managed to put in symbols and footprints for the detector diode, and the LTC6269. Then to ERC which had me stumbling over fictitious power flags. Got them in place and finally was able to see my parts in layout. I'm far from done, but I'm making some slow progress. I have the PIN diode and 3 of the LTC parts in place. Sort of trying to stay with 0603 parts, and up. It's not that easy to cram everything in place. I like to use short stubs between pads and a via. They take up space, but they are a lot easier to rework, because you can cut the trace to the via.

Work in progress...

SMD layout is challenging...

Well, foo, forgot to put in the guard ring in the first stage. Time for a little rip up. At least there is some room to play with that big SOIC. The DFN10 is only 3x3 mm. It makes the 0603's look so big.

 

[graham-xrf]

Finally, something I can speak to. The three of you were beginning to give me an inferiority complex with all your technical talk. PSU's and ADC's and zero offsets, oh my!

You will have no problem melting lead. I often use cans from veggys for molds. I made a melting pot from a veggy can by running a coat hanger loop though a couple of holes. The lead will melt easily with your camping stove or with a propane torch. I don't usually bother with flux, I just scrape off the dross until I have clean metal. If you want to use flux, soldering flux will work. If you don't use flux, there is no need to work outside.

If I put in some acid flux, of the sort usually used to put on copper plumbing joints before soldering, will the lead end up soldered to the inside of the can? That may not matter a whole lot, but it would be nice if the lead would come free of the can.

 

[RJSakowski]

If I put in some acid flux, of the sort usually used to put on copper plumbing joints before soldering, will the lead end up soldered to the inside of the can? That may not matter a whole lot, but it would be nice if the lead would come free of the can.

I would use a rosin flux. But it you heat the can to a red heat, it will form a black oxide coat and lead won't stick to it. Throw the can on your wood fire or better, on a bed of coals. It will blacken nicely. You will want to do that anyway since there will be an epoxy coat on the inside of the can to protect the former contents. In any event, the can is single use and can be peeled off.

 

[homebrewed]

Spent some quality time wrestling with KiCAD. Managed to put in symbols and footprints for the detector diode, and the LTC6269. Then to ERC which had me stumbling over fictitious power flags. Got them in place and finally was able to see my parts in layout. I'm far from done, but I'm making some slow progress. I have the PIN diode and 3 of the LTC parts in place. Sort of trying to stay with 0603 parts, and up. It's not that easy to cram everything in place. I like to use short stubs between pads and a via. They take up space, but they are a lot easier to rework, because you can cut the trace to the via.

Work in progress...
View attachment 437843
SMD layout is challenging...

Well, foo, forgot to put in the guard ring in the first stage. Time for a little rip up. At least there is some room to play with that big SOIC. The DFN10 is only 3x3 mm. It makes the 0603's look so big.

There's something about your input configuration that has me a bit puzzled. It looks like the input bias voltage to the detector is routed through R1, and that's the same node to the TIA's virtual ground (through C1). That same node connects to (I think) the anode of the detector. Its cathode is at ground. Therefore, current pulses through the diode result in a negative current pulse into the TIA. Is my analysis correct or am I overlooking something?

Not that the topology matters all that much -- due to the NFB, bias voltage on the detector is unaffected by current pulses. But it's different enough that I would suggest running some simulations to make sure the circuit is stable.

 

[graham-xrf]

Spent some quality time wrestling with KiCAD. Managed to put in symbols and footprints for the detector diode, and the LTC6269. Then to ERC which had me stumbling over fictitious power flags. Got them in place and finally was able to see my parts in layout. I'm far from done, but I'm making some slow progress. I have the PIN diode and 3 of the LTC parts in place. Sort of trying to stay with 0603 parts, and up. It's not that easy to cram everything in place. I like to use short stubs between pads and a via. They take up space, but they are a lot easier to rework, because you can cut the trace to the via.

Work in progress...
View attachment 437843
SMD layout is challenging...

Well, foo, forgot to put in the guard ring in the first stage. Time for a little rip up. At least there is some room to play with that big SOIC. The DFN10 is only 3x3 mm. It makes the 0603's look so big.

My first thought is .. yep, OK, this is great! I would also be celebrating laying out stuff in KiCad.
Getting to the layout. The bias arrangement looks wrong.
Sure, one end of the diode connects to C1.
The other side of the diode is where the 100K goes, and that side should also be decoupled to 0V by (carefully chosen) capacitor.
Following the rat's nest, it looks like it finds GND instead.

That place on one end of C2 may well be network correct so far as the rat's nest is concerned, but it is, in fact, right in the middle of the high gain feedback network, connected to one end of the compensation capacitor. This is on a thing that has gain up to 4GHz!
The input is on but a tiny little gap next to the output. Are you really pressed for space? Why not use what you need?

Make the 1pF capacitor be two 2.2pF capacitors in series. That way, you get something like the value you intend, and isolate the output track, stopping the stray capacitance from the layout and over R4 from going right past your component, and deciding for you. Put a thin ground track right under R4, even if you have to use a bigger resistor.

You need to shunt the electric field around the feedback resistor to a ground trace under, and top plane around, with enough gap. This is an RF device, if given a chance, and you will want to be in control of the highest frequency it can operate at. I know you are into radar, and LNAs. Think of using the same techniques here, until you get a bit further from the TIA input.

Refer to Linear Tech data sheet page15, and see Figure 6.
Have that output only see the end of a resistor. and one end of a compensation series capacitor pair.

It is quite hard to improve on the layout shown on Page 16, Figure 8 that shows how to implement the guard ring.
This you will need, especially if you have ambitions to use a bias like 30V.
The input resistance of the opamp is extreme. More than 1000GΩ !! The input bias current is only +/- 3fA
That is only 18700 electrons/sec !
In this case, FR4 does not look much like an insulator. You might get it to about 5 to 10GΩ if dry, and very clean.
This device will respond to currents across an FR4 PCB, like you were putting components onto a partially conductive soup.

The guard ring will stop all that! The whole reason I chose the SO8 package with only one opamp in it was because it allowed (only just), a thin track to go between the pins for the guard ring. The signal from the diode, and the track coming from the feedback can "drop in" to the middle of the ring, and all other currents on the board will stop at the ring.

Decoupling the biased side of the diode needs something like 100nF in parallel with something like up to 1uF of 2.2uF
Listen to Mark @homebrewed 's advice earlier about choosing capacitors that don't make way more signal from microphonic vibration effects than the signal you are trying to capture. In that particular place on the other end of the diode, the decoupling capacitor will add it's piezoelectric contribution in series with the photon pulse path.

Here it occurs to me to ask. If the front of the diode is facing the incoming X-rays, in a assembly with shielding and radioactives, are not the electronics to be on the other side of the board?

[Edit: Did you make the footprint for the X100-7 yourself, or was it just available from somewhere? If it's OK, maybe post it here?
Also - sorry I did not see your last sentence (text not expanded). Clearly you already got to the guard ring issue! ]

 

[WobblyHand]

There's something about your input configuration that has me a bit puzzled. It looks like the input bias voltage to the detector is routed through R1, and that's the same node to the TIA's virtual ground (through C1). That same node connects to (I think) the anode of the detector. Its cathode is at ground. Therefore, current pulses through the diode result in a negative current pulse into the TIA. Is my analysis correct or am I overlooking something?

Not that the topology matters all that much -- due to the NFB, bias voltage on the detector is unaffected by current pulses. But it's different enough that I would suggest running some simulations to make sure the circuit is stable.

I think things are ok, the diode will generate a small negative pulse. This circuit is similar to what I simulated, simply removing the diode model. After the first stage the signal gets inverted again in later stage. Honestly never done TIA stuff, so I'm expecting some ups and downs.

 

[WobblyHand]

My first thought is .. yep, OK, this is great! I would also be celebrating laying out stuff in KiCad.
Getting to the layout. The bias arrangement looks wrong.
Sure, one end of the diode connects to C1.
The other side of the diode is where the 100K goes, and that side should also be decoupled to 0V by (carefully chosen) capacitor.
Following the rat's nest, it looks like it finds GND instead.

That place on one end of C2 may well be network correct so far as the rat's nest is concerned, but it is, in fact, right in the middle of the high gain feedback network, connected to one end of the compensation capacitor. This is on a thing that has gain up to 4GHz!
The input is on but a tiny little gap next to the output. Are you really pressed for space? Why not use what you need?

Make the 1pF capacitor be two 2.2pF capacitors in series. That way, you get something like the value you intend, and isolate the output track, stopping the stray capacitance from the layout and over R4 from going right past your component, and deciding for you. Put a thin ground track right under R4, even if you have to use a bigger resistor.

You need to shunt the electric field around the feedback resistor to a ground trace under, and top plane around, with enough gap. This is an RF device, if given a chance, and you will want to be in control of the highest frequency it can operate at. I know you are into radar, and LNAs. Think of using the same techniques here, until you get a bit further from the TIA input.

Refer to Linear Tech data sheet page15, and see Figure 6.
Have that output only see the end of a resistor. and one end of a compensation series capacitor pair.

It is quite hard to improve on the layout shown on Page 16, Figure 8 that shows how to implement the guard ring.
This you will need, especially if you have ambitions to use a bias like 30V.
The input resistance of the opamp is extreme. More than 1000GΩ !! The input bias current is only +/- 3fA
That is only 18700 electrons/sec !
In this case, FR4 does not look much like an insulator. You might get it to about 5 to 10GΩ if dry, and very clean.
This device will respond to currents across an FR4 PCB, like you were putting components onto a partially conductive soup.

The guard ring will stop all that! The whole reason I chose the SO8 package with only one opamp in it was because it allowed (only just), a thin track to go between the pins for the guard ring. The signal from the diode, and the track coming from the feedback can "drop in" to the middle of the ring, and all other currents on the board will stop at the ring.

Decoupling the biased side of the diode needs something like 100nF in parallel with something like up to 1uF of 2.2uF
Listen to Mark @homebrewed 's advice earlier about choosing capacitors that don't make way more signal from microphonic vibration effects than the signal you are trying to capture. In that particular place on the other end of the diode, the decoupling capacitor will add it's piezoelectric contribution in series with the photon pulse path.

Here it occurs to me to ask. If the front of the diode is facing the incoming X-rays, in a assembly with shielding and radioactives, are not the electronics to be on the other side of the board?

[Edit: Did you make the footprint for the X100-7 yourself, or was it just available from somewhere? If it's OK, maybe post it here?
Also - sorry I did not see your last sentence (text not expanded). Clearly you already got to the guard ring issue! ]

I will post my latest layout, there are changes. Added the guard ring, although I was a little confused on doing it. There's a lot of nuance to this, and I'm far from an expert. Have included the AD8655 to the schematic and the integrator. It's getting very busy, with 0603 parts. They are quite large compared to the LTC6269 DFN10 packages. I am practically at my limit with 0603's these days. If I go with 0402s I will have to get it assembled, because I can't place the parts.

Yes, I drew the part footprint for the PIN diode. Hope I got it right. I can post it when I get to my desk. Took maybe 15 minutes to create, wasn't hard. Simply used the footprint editor and drew from the diode datasheet. Won't be IPC grade, however. After that I made a symbol and footprint for an AD8655. Looks home made, but it will allow me to wire it in. Need to find a symbol and footprint for the ADC next. Once I figured it out, making custom parts wasn't that bad.

I'm not thinking this board is anywhere near final configuration. I'd be happy just to see it work at all. The silk screen will show V0.1. I haven't thought about shielding at all. It's just a prototype. I'm going to see if I can find a bigger package version for the 6269. It's really tough to route with two wiring layers.

Our automotive radars were 6 or 8 layers and used parts down to 0201s. I'm nowhere near a dense layout. On the other hand, we used sophisticated auto routers.

I found the auto renumbering reference designators in layout was a disaster. I couldn't believe it screwed up so bad, putting decoupling cap values into the TIA feedback. Fortunately there was the undo button. That really surprised me to see the total mess it created.

Assigning footprints is quirky in KiCAD, sometimes I get the library symbol to show up, and other times I have to move the cursor outside of the window before it becomes visible and selectable. It's not predictable, so I guess it keeps one on one's toes. Hate to fall asleep at the computer, so is this supposed to help?