Needing more than a spark test?

[rabler]

Note also that your trace at the bottom of the board may be too close to the edge. 0.2mm is spec'd min, I use 0.25mm. Something else I've run into is minimum text size on the silkscreen.

Here's what my latest version looks like with mostly 0805's, some 0603's for tvs diodes. (Not sure I'll actually have this one fabbed). There are some tight spaced parallel traces, but those are low impedance, low speed (100Hz or less) traces.

 

[WobblyHand]

@WobblyHand
Here is a link to jlcpcb's tech specs: https://jlcpcb.com/capabilities/pcb-capabilities
I tend to set the spec's to slightly more than the given minimums (several youtube discussions on this can be found, e.g., eevblog).
I use .55/.25 for a minimum via size, .1mm for a minimum trace width and trace to trace clearance on 4 layer boards. I use .25mm as my default trace width, typically .5mm routed power/ground traces..

Also, not sure of your circuit speed, but if the lines to the left of U5 are of any speed, I'd suggest spacing the traces further apart. While the pcb design rules give a minimum, cross coupling can be problematic and the minimums are for fan out at small parts but not great for long parallel runs. I use 1mm as a rule of thumb. 3x the trace width is apparently a common recommendation. I'm throwing this out as what I've picked up for good basic design practices, if you have more experience then let that lead you.


Are you considering a split ground plane? I've heard pros and cons on that. I made ground plane cuts around my ADC but was careful to make sure I didn't route any lines over the cuts due to impedance changes causing reflections.

0402s? That's smaller than I would attempt if assembling it by hand using a hot air rework station.

Thanks for the link to jlcpcb. And for the line spacing on U5, those are digital lines, the output of the ADC, Sample rate is about 500 KHz to 1 MHz, I'll spread them out a bit. I have a split power plane for the front end, and a continuous analog ground plane. I also have a digital ground plane for the Teensy, and a digital and analog ground around the ADC that I have yet to bond together. Right now the ADC grounds are separate. I may use a geometric patch to join them, probably on the back, connected to the planes though vias. I think that is the old school way of doing it.

I don't know how the heck to get this board done without resorting to one or two 0402's. They are going to be tough. If I could fit in an 0603, I'd be a lot happier. When I can, I through in a couple of bigger parts, to throw myself a bone.

Ran a DRC and the only errors now are my missing ADC analog & digital zones, as well as my digital ground zone for the Teensy, which isn't too bad. Been at this all day though...

Time to stop, I noticed that KiCAD decided to reroute some digital line in an insane way. I don't know how that happened, but this program seems to do strange things when stuff gets dense. The route is kind of comical actually.

Before I started moving the traces apart, that route didn't look that way! I didn't do that!

 

[homebrewed]

I will have to use 0402 parts in close to the ADC, because 0603's are BIG.

I get the desire to keep sizes to a minimum but I have chosen to just live with the size, given the ability to (relatively easily) solder 0603's down. It usually is possible to juggle spacings etc to accommodate them. I laid out my ADC board with 0603's or larger. The latter were just a few 1206's for the higher-capacitance bypass caps.

This particular application isn't particularly high-frequency so layout requirements can be relaxed some. Serial ADC's running at the same sample rate are a bit more challenging because the serial clock has to be higher by at least 16X the maximum-desired sample rate.

The most challenging layout issues are reducing crosstalk between the digital and analog signal blocks.

 

[homebrewed]

I finished assembling all the different parts of my **new and improved** source design, which eliminates the aluminum ring and moved the sources further out to prevent bogus counts from the carrier disks. I installed it into my test setup and observed a noticeable improvement in the purity of the spectrum when analyzing my 1cm^3 iron elemental reference. Just two peaks, one at lower energy from system noise and one from the iron:


This spectrum was acquired using the Teensy4.0's on-chip ADC, whose ENOB is somewhere around 10 bits when it's maxed out at 360KSPS. I will be working on changing my program to use my 16 bit 1MSPS ADC. Hopefully that will help to tighten up the energy distribution: but the ultimate limitation is going to be the detector's energy resolution. Past that, improvements will be software-based using deconvolution schemes as described by the Theremino team.

At this point it seems I have managed to eliminate the "aluminum glare" from my original focus ring design. I still need to do a background spectrum to see if an iron peak pops up -- since the Am241 is on a steel carrier disk, that will tell me if the focus ring geometry is really right or not.

Some may have noticed the red trace on the plot. That's a gaussian-filtered version of the raw MCA data. If not done correctly the filtered version can be shifted relative to the input array but I think I got it right.

 

[homebrewed]

Driver code for my AD7667 ADC board can be found here, although it's mixed in with stuff meant to test it out. @WobblyHand Bruce may find it more useful at this point. The ISR stores acquired data as uint16_t_in a circular buffer but, given the Teensy4.x speed and built-in FPU, there isn't much additional overhead needed to do it in floating point. That's where I'm headed, to see what improvement can be had in the XRF spectrum.

The driver code is written in C, not C++ so it really isn't useful as a generic Arduino library. That may happen at some point but I'm kind of old-school, haven't really taken the time to dive into C++ too much yet.

 

[graham-xrf]

Time to stop, I noticed that KiCAD decided to reroute some digital line in an insane way. I don't know how that happened, but this program seems to do strange things when stuff gets dense. The route is kind of comical actually.
Before I started moving the traces apart, that route didn't look that way! I didn't do that!

Software of any kind is always capable of "doing strange things", particularly when every single thing it does is in an arrangement unique to the user's project. Still, KiCad is now used on an industrial scale, and has at least a couple of decades of bug removal.

I would think that the (very funny ) route was maybe forced on it by some rule you set, or possibly, even with the default set of rules, you closed off a more boring, but functional route where you forced a component position.
-------------------------------------
Re: KiCad V7. Do not allow an upgrade from V6 just yet!

My User Global library is just not there any more. For me, that is not of any great consequence. The ADC was the only part in it, and it survives in the project embedded copy. I can do a copy-paste and save it again. I might just keep a local library. I know a user can make a User Global Library, but I must have done it wrong, or maybe it is still there, but needs it's path mentioned somewhere.

In my home folder, in the ~/.local/share/kicad, There is a 6.0, and now a 7.0

 

[graham-xrf]

I get the desire to keep sizes to a minimum but I have chosen to just live with the size, given the ability to (relatively easily) solder 0603's down. It usually is possible to juggle spacings etc to accommodate them. I laid out my ADC board with 0603's or larger. The latter were just a few 1206's for the higher-capacitance bypass caps.

I do agree! We can surely just take all the space we need, unless we already bought the box it has to fit.

This particular application isn't particularly high-frequency so layout requirements can be relaxed some. Serial ADC's running at the same sample rate are a bit more challenging because the serial clock has to be higher by at least 16X the maximum-desired sample rate.

I would caution against the relax!
The devices Bruce and I are using can work at GHz! Even if the fundamental frequencies they pass do go very low, the spectral content from edges and waveform shapes are preserved, and they can oscillate at RF frequencies. The layout around them has to be appropriate to the frequencies they can amplify, not those the project happens to use.

The most challenging layout issues are reducing crosstalk between the digital and analog signal blocks.

Yes, I always thought it would be so. and I have yet to run into the same thing!
Your spectrum for iron really is looking better!

X-rays from iron are at 6.4KeV, and 7.05KeV. So on a roughly visual estimation, the droop of low counts between those peaks would be at around (say) 3KeV. Now mentally split that again, and we are already at the point where even 1.48KeV aluminium response would be. Not only is the pulse height low, the probability of the X100-7 responding is about 2% or 3%.

The large count of small waveforms, is likely system noise. Given that we do not expect to be detecting any elements of atomic number less than 11, and we have small chance of seeing, or needing to see, sodium Na, one could simply disallow energies less than 900eV from the plot.

It would be great if, in the end, we get to see magnesium (1.25KeV and 1.3KeV) and aluminium (1.48KeV and 1.55KeV). The low probability aside, X-rays at that energy are definitely competing with the noise.

 

[graham-xrf]

@WobblyHand
Bruce, I know we find it convenient to use two LTC6269s in a single package, but the circuit with integrator uses three. This is only because I (lazy), just copied and pasted one of the LTC6269s already on the simulation schematic.

I am guessing that you might well have already put something else in to do the integration loop that removes offsets. Definitely, that is a place where we can have something with a much lower GBW. I have simulated the resistor from integrator into the final gain stage (R10), changing from 100K to 47K, and then to 22K. It does reduce the offset from nano-volts to pico-volts, but this is simply not needed.

Anyway, I think we should not be using a RF-capable LT6269 in a feedback loop onto the main signal. It could make layout even more challenging!

 

[rabler]

Before I started moving the traces apart, that route didn't look that way! I didn't do that!

Under the "Route" tab, you can change the 'Interactive Route Settings' to something other than 'walk around' to stop this behaviour, but it does make drawing traces a bit more difficult.

 

[rabler]

@graham-xrf
I started migrating my design pictured above (last page?) to Kicad V7. The custom schematic symbols came through fine, but the layout footprints were lost. I had to re-enter them from the "manage libraries". Then, for some reason,
all my custom footprints complained in the DRC about SMD vs through hole. I had to manually change each custom part in the layout to be SMD through it's properties. Brief look doesn't show how that is stored in the footprint.

Struggling with how to best organize custom parts. I started by naively following the instructions included with most parts downloads. I don't like the result where each such part is a separate library. I find that hard to locate as the libraries are sorted alphabetically so they get scattered through the list which is otherwise by part type rather than part number. I'd rather have one library of my custom parts. I accomplished that by copying all my custom footprints to a common file folder. I did have to rename a few footprints from a package identifier to a part number like name. If anyone has a better way of managing custom parts I'd like to hear about it.