Needing more than a spark test?

Yes, it's DGND. Once I connected DGND and AGND on the schematic, the PCB design program treated both the same in terms of the rat's nest so it would be really easy to screw up the layout, at least in terms of preserving the desired "star" connection. I _think_ I got it right.

Speaking of layout issues, I was considering separating OGND from DGND but due to the way the ISR runs the ADC, either the digital section is running or the output section is running: but not both at the same time. So it seems to me that it should be OK for them to share the same ground.

Regarding the zilch improvement in noise, well, now we know that going to the trouble of doing those mods isn't worth it. But it appears to me that noise and a ~13 count offset are two different issues. One suggestion: use a DVM to measure the DC voltage coming out of the opamp buffer to see what it's doing.
The offset is coming out of the buffer. At the input I measure 0mV relative to the op amp ground. At the output of the buffer, I measure 0.6mV on my DVM, and I am measuring 15.25 counts at the ADC. Which is 0.58mV. It appears to be coming out of the buffer. My buffer offset is wandering slowly upward. When it is stone cold is is at 9-10 counts, when the die heats it is 13-15 counts.
 
The offset is coming out of the buffer. At the input I measure 0mV relative to the op amp ground. At the output of the buffer, I measure 0.6mV on my DVM, and I am measuring 15.25 counts at the ADC. Which is 0.58mV. It appears to be coming out of the buffer. My buffer offset is wandering slowly upward. When it is stone cold is is at 9-10 counts, when the die heats it is 13-15 counts.
Good info!

My pulse processor includes a baseline compensation function that (if implemented correctly) should take care of slow drift like what you're seeing. The code also has an option to force a system calibration, which at this time is exclusively aimed at baseline correction.
 
Good info!

My pulse processor includes a baseline compensation function that (if implemented correctly) should take care of slow drift like what you're seeing. The code also has an option to force a system calibration, which at this time is exclusively aimed at baseline correction.
The buffer should have lower offset than it is exhibiting I think. Might redo the solder joints and attempt to clean it more. This isn't dissimilar metal stuff is it?
 
The RMS noise is fairly decent, wandering around 1.1 to 1.6 counts, it really doesn't get too much better than that. The offset, is sitting at the absolute max over temperature rating, and it's about 22C here, which makes little sense. AD8655 offset spec is 550uV max over -40 to +125C. I'm getting 580uV (15.25 counts) at a gain of one.
 
Yes, it's DGND. Once I connected DGND and AGND on the schematic, the PCB design program treated both the same in terms of the rat's nest so it would be really easy to screw up the layout, at least in terms of preserving the desired "star" connection. I _think_ I got it right.
Hi Mark
Yes indeed, DGND pin is a very special sort of digital ground, and it does get connected to GND at the ground plane right under the chip. The state of the SAR switched capacitor array is transferred into a register in a low energy manner, and the internal star point is GND, connected to DGND.
DGND is noise free, returning currents from DVDD, and does not share significant energy with OGND.

The interface digital circuits are powered from OVDD, returning to OGND. These two are separately provided for the purpose of reading out the result to eternal digital devices without any of the associated currents becoming involved with the ADC measurement front end.

Speaking of layout issues, I was considering separating OGND from DGND but due to the way the ISR runs the ADC, either the digital section is running or the output section is running: but not both at the same time. So it seems to me that it should be OK for them to share the same ground.

DGND and OGND are deliberately provided separately, for exactly the reason that they never do (share the same ground). The whole idea is not to pollute the sensitive capacitor SAR array, and its comparator, with any clocking, digital data, and other currents associated with the data interface, and OGND. One should not casually decide to subvert this aspect of the ADC design. If it was OK to join OGND to DGND, it would have been done in the chip.

This is why I made the supplies be independent, and isolated. Yes, I derive the analog supply from the 3.3V, and I use a LDO regulator, but the low power high frequency isolation transformer barrier ensures that no currents involved with reading out digital data can ever run in, nor return to GND nor DGND. I once considered it might be easier to use a couple of AA batteries!

If one simply uses the same supply from the computer circuits, regulated down as necessary, and hope to supply the ADC from it, then necessarily, the GND, DGND and OGND all end up connected together somewhere. This bypasses the design arrangement that provides the separate OGND for digital interface transfers.

Nor can it be about when one or the other is not using it simultaneously. If the computer ground finds it's way to the analog GND, then it, and it's noise, and the voltage developed from the return current across the ground plane, and 0V wire going to the computer, will be there, regardless of when you happen to be transferring data.
 
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The RMS noise is fairly decent, wandering around 1.1 to 1.6 counts, it really doesn't get too much better than that. The offset, is sitting at the absolute max over temperature rating, and it's about 22C here, which makes little sense. AD8655 offset spec is 550uV max over -40 to +125C. I'm getting 580uV (15.25 counts) at a gain of one.
That amount of offset does seem high. The opamp's ground is a little way from the ADC's analog ground connection. Perhaps there's more voltage drop on the ground plane than we realize?
 
That amount of offset does seem high. The opamp's ground is a little way from the ADC's analog ground connection. Perhaps there's more voltage drop on the ground plane than we realize?
It may be that the current that is doing it does not all belong to the analog opamps.
 
It may be that the current that is doing it does not all belong to the analog opamps.
Quite possible. That's why one attempts to separate the grounds and supplies.

Could be a defective or counterfeit part too. I bought some "ADI" parts from questionable sources and they turned out to be non-performant. They sort of worked, but not very well. Was around 2021. I then sourced some from an on shore source and those were ok.

But these buffers were from a legit source. It's worth a try, I have 3 of them. It's a long shot though...
 
When I suspected temperature related problems I would test different parts of a circuit with a Q tip that had been sprayed with cold freeze. Just spraying with the can nozzle or tube is too extreme to provide localized sensitivity measurements. A soldering iron tip can do the same thing but you run the risk of unsoldering things, or damaging nearby plastic components.

In terms of the Seebeck effect, most dissimilar-metal situations on a PCB are balanced. For every copper-solder interface you've got a solder-copper interface to balance it out. This happy situation is disturbed by thermal gradients. The Seebeck constants for lead and copper are pretty close -- copper's is 6.5mv/K and lead is 4mv/K, according to one paper I found online. That paper didn't have a value for tin. For comparison, the iron-constantan thermocouple combines iron @19mv/K and constantan @-35mV/K.

Thing is, even if it looks like it wouldn't take much of a gradient to get a 500uv difference between 6.5mv/K and 4mv/K, the interfaces are VERY close together -- think IC pin to solder, then the same solder pool to the copper PCB trace right underneath it. Not much separation, physically and thermally speaking. So while some offset is theoretically possible, I don't think that is what is going on here.
 
From Analog.com 404 "page not found" crash, there is a temperature sensor (Heath-Robinson type) feeding back into a Analog "404" quad flatpack, looking like it is doing something a little similar to Figure 30 on Page 20 of the AD7667 datasheet. :)

Analog404.gif
 
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