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- Feb 25, 2021
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I haven’t researched this much. But I think there is a strong counter argument to be made on the cost/complexity issue. The classic implementation is going overboard on encoder resolution, driving a high interrupt rate, creating a lot of overhead in servicing a frequent interrupt, to give a reasonable fidelity to step timing. This runs into upper limits on encoder vs rpm.
Currently the classic algorithm is fire off a step if justified at the current encoder pulse. Change he algorithm slightly, to determine if a step is warranted before the next encoder pulse. If so interpolate at what estimated time that step should occur.
Measuring the time interval between two encoder pulses is trivial if you use a microcontroller with input event timing capture hardware. Subtraction with attention to timer wraps. At a cursory glance, the pico doesn’t qualify, but the teensy does. Simplistically just use the previous interval as a predictor of the next interval.
PLLs and etc etc are way overkill.
If you can interpolate timing to 1/10 of the encoder interval then you could use an encoder with one tenth the resolution, and thereby reduce the pulse rate on the encoder by a factor of 10. Realistically you can get 1 uS (1MHz) clocking easily, but even a 10uS capture clock resolution is sufficient.
Could you then use a 512 pulse/turn encoder to the same effect as the 4096? There is a lower bound on this as the acceleration/deceleration of the spindle becomes problematic. But for a reasonable spindle mass it would be interesting to measure/calculate an upper bound on speed changes over 1/512 of a revolution, that is still less than 1 degree. I doubt it going to be more variation than the 2 out of 3 pulses in the above, although that is an extreme case. The point is both schemes have timing error. pulse - pulse -skip can be modeled as a timing error. Can I use a 512 pulse encoder with timing interpolation and beat that error, even in the presence of acceleration? TBD but I would guess it could.
At 1000rpm, 512 pulse per rev is 117 us/pulse if my late night math is correct. So a 10uS capture clock resolution would still give a factor of 10 improvement on the (virtual) encoder resolution, performance of a 4096 pulse encoder with 1/10 the interrupt rate for the simple cost of waiting for a timer. If that timer is interrupt based (vs spin wait) that doubles the number of interrupts so we get 1/5th rather than 1/10th the interrupt rate.
Normally I would look at the desired delay and spin wait vs schedule a delay timer depending on what is more efficient.
No where in this does the complexity approach justifying an FPGA if a micro with event timing capture is used. Note I picked 512 as that is actually 1/8 of 4096, makes dividing the interval a simple matter of bit shifting. If I use a 512 pulse encoder with timing resolution justifying 16 virtual pulses (really 15+1Real) then I have a virtual 8192 pulse encoder, and beat the 4096 pulse encoder‘s effective resolution, at a much lower processor load. I’m now at skip-skip-pulse-skip-skip-pulse for what was the previous 2 out of 3. Less peak strain on your spring (maybe less chance of a loststep if using a cheap stepper?) Then, could I deal with higher RPMs where the classic system would die sooner on the higher interrupt rate?
Currently the classic algorithm is fire off a step if justified at the current encoder pulse. Change he algorithm slightly, to determine if a step is warranted before the next encoder pulse. If so interpolate at what estimated time that step should occur.
Measuring the time interval between two encoder pulses is trivial if you use a microcontroller with input event timing capture hardware. Subtraction with attention to timer wraps. At a cursory glance, the pico doesn’t qualify, but the teensy does. Simplistically just use the previous interval as a predictor of the next interval.
PLLs and etc etc are way overkill.
If you can interpolate timing to 1/10 of the encoder interval then you could use an encoder with one tenth the resolution, and thereby reduce the pulse rate on the encoder by a factor of 10. Realistically you can get 1 uS (1MHz) clocking easily, but even a 10uS capture clock resolution is sufficient.
Could you then use a 512 pulse/turn encoder to the same effect as the 4096? There is a lower bound on this as the acceleration/deceleration of the spindle becomes problematic. But for a reasonable spindle mass it would be interesting to measure/calculate an upper bound on speed changes over 1/512 of a revolution, that is still less than 1 degree. I doubt it going to be more variation than the 2 out of 3 pulses in the above, although that is an extreme case. The point is both schemes have timing error. pulse - pulse -skip can be modeled as a timing error. Can I use a 512 pulse encoder with timing interpolation and beat that error, even in the presence of acceleration? TBD but I would guess it could.
At 1000rpm, 512 pulse per rev is 117 us/pulse if my late night math is correct. So a 10uS capture clock resolution would still give a factor of 10 improvement on the (virtual) encoder resolution, performance of a 4096 pulse encoder with 1/10 the interrupt rate for the simple cost of waiting for a timer. If that timer is interrupt based (vs spin wait) that doubles the number of interrupts so we get 1/5th rather than 1/10th the interrupt rate.
Normally I would look at the desired delay and spin wait vs schedule a delay timer depending on what is more efficient.
No where in this does the complexity approach justifying an FPGA if a micro with event timing capture is used. Note I picked 512 as that is actually 1/8 of 4096, makes dividing the interval a simple matter of bit shifting. If I use a 512 pulse encoder with timing resolution justifying 16 virtual pulses (really 15+1Real) then I have a virtual 8192 pulse encoder, and beat the 4096 pulse encoder‘s effective resolution, at a much lower processor load. I’m now at skip-skip-pulse-skip-skip-pulse for what was the previous 2 out of 3. Less peak strain on your spring (maybe less chance of a loststep if using a cheap stepper?) Then, could I deal with higher RPMs where the classic system would die sooner on the higher interrupt rate?
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