I wrote up some Verilog and a test bench to go with it, and implemented it in a Xilinx XC9536XL (their smallest 3.3V CPLD). The zip file attached is for Xilinx' ISE software (which you can download for free at xilinx.com, but you will have to search to find it because it's obsolete since 2013). The newer Vivado suite doesn't support CPLDs or even the older FPGA families.
I don't have the faintest idea if this is right, but it's based on the Simon schematic and hopefully I didn't hook anything up incorrectly. It at least compiles and simulates.
Be gentle, it's been a few years now since I wrote any Verilog....
I don't have the faintest idea if this is right, but it's based on the Simon schematic and hopefully I didn't hook anything up incorrectly. It at least compiles and simulates.
Be gentle, it's been a few years now since I wrote any Verilog....